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monolithic synchronous voltage-to-frequency converter ad652 rev. c in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures f u ll-sc ale fr e q uenc y (up t o 2 m hz) set by e x t e rnal sy st em clock ex tremely low l i nearit y error ( 0 .005% m a x a t 1 mhz fs, 0.02% ma x a t 2 mhz fs) no critic al e x t e rnal c o mponen ts r e quir e d a c cur a t e 5 v r e f e r e nc e v o ltag e l o w drif t (25 p p m/ c ma x) dual- or single - sup p ly oper a t i o n v o ltage or curr ent input mil - std - 883 compliant v e rsi o ns a v ailabl e pr oduc t description the ad652 sy nc hr o n o u s v o l t a g e-t o -f r e q u en c y co n v er t e r (svfc) is a p o w e r f u l b u i l din g b l o c k fo r p r e c isio n a n a l og-t o- dig i t a l con v ersio n , o f f e r i n g typ i cal n o nlin ea r i ty o f 0.002% (0.005% maxim u m) a t a 100 kh z o u t p u t f r eq uen c y . th e in h e r - e n t m o n o t o n i ci ty o f th e tra n sf e r fun c ti o n a n d wi d e ra n g e o f c l oc k f r eq ue n c ie s allo w th e co n v e r si o n tim e a n d r e so l u ti o n t o b e o p t i mi ze d for sp e c if ic a p pli c a t io n s . the ad652 us es a va r i a t io n o f t h e c h a r g e -bal ancin g t e c h niq u e to p e r f or m t h e c o n v e r s i on f u nc t i on . t h e a d 6 5 2 u s e s an ext e r n al clo c k to def i n e t h e f u l l - s c ale o u t p ut f r e q uen c y , ra t h er t h an rely i n g on t h e s t abi l it y of an e x te r n a l c a p a c i tor . t h e re su lt i s a more st abl e , more l i ne ar t r a n s f e r f u nc t i on , w i t h s i g n i f i c an t a p plic a t ion b e nef i ts in b o t h sing le- an d m u l t icha n n el sy stem s. ga in dr if t is mi nimi ze d usin g a p r e c isio n lo w dr if t r e fer e n c e an d l o w tc , on - c h i p , t h i n - f i l m s c a l i n g re s i stor s . f u r t he r m ore, ini t ial ga in er r o r is r e d u ced t o l e s s tha n 0.5 % b y th e us e o f las e r - wa fer - t r immi n g . the a n alog an d dig i t a l s e c t io n s o f th e ad652 ha v e been desig n e d to a l lo w o p er a t i o n f r o m a sin g l e -e n d e d p o w e r s o ur ce, sim p lif y in g i t s u s e wi th is ola t e d p o w e r s u p p lies. the ad652 is a v a i lab l e in f i ve p e r f o r ma n c e g r ades. th e 20-lead plc c - p a ck a g e d jp and kp g r a d es a r e sp e c if ie d fo r o p er a t ion o v er t h e 0c t o +70c co mm ercial t e m p er a t ur e ra n g e . th e 16-le ad cerdi p -p ack a ge d a q a nd b q g r ades a r e sp e c if ie d fo r o p era t ion o v er t h e ?40 c t o +85c i n d u s t r i al tem p er a t ur e ra n g e . th e ad6 52sq is a v a i la b l e fo r o p era t io n o v er t h e f u l l ?55c t o +125c ext e nded t e m p era t ur e ra n g e . produc t hi ghlight s 1. the us e o f a n e x t e r n al clo c k t o s e t t h e f u l l -s c a le f r e q uen c y al lo ws t h e a d 6 52 t o achie v e li n e a r i t y an d st a b ili t y fa r sup e r i or to ot he r mo no l i t h i c v f c s . by u s i n g t h e s a m e cl o c k t o dr i v e the ad652 a nd s e t t h e co un tin g p e r i o d (thr o u g h a sui t ab le divid e r), co n v ersio n ac c u rac y is ma in t a ine d i n d e p e nd e n t of v a r i a t i o ns i n cl o c k f r e q u e nc y . 2. the ad652 sy nc hr o n o u s vfc r e q u ir es o n l y o n e ext e r n al c o m p o n en t ( a n o n c ri ti cal i n t e gra t o r ca pa c i t o r) f o r op e r a t i o n . 3. the ad652 in c l udes a b u f f er ed , acc u ra t e 5 v r e fer e n c e . 4. the ad652 s c l o c k in p u t is t t l a nd cm os com p a t i b le and ca n als o be dr i v en b y s o ur ces r e f e r r ed t o th e n e ga ti v e p o w e r supply . t h e f l e x ibl e op e n - c o l l e c t or output st age prov i d e s suf f i cien t c u r r en t sink in g ca p a b i li ty fo r t t l and cmos log i c, as w e l l as f o r o p tical co u p lers a n d p u ls e tr a n sf o r m e rs. a c a p a c i tor - pro g r a m m a bl e o n e - s h ot i s prov i d e d f o r s e l e c - t i on of opt i m u m output pu l s e w i d t h f o r p o we r re d u c t i o n . 5. the ad652 can als o be co nf igu r ed f o r us e as a syn c hr o n o u s f/v co n v er t e r fo r is ola t e d a n al og sig n al tra n smis sio n . 6. the ad652 is a v a i lab l e in v e rsio n s co m p l i an t wi t h mils td-883. ref e r t o th e anal og devices m i l i ta r y p r o d uc ts d a tab o ok o r c u r r en t ad652/883b da ta sh eet f o r det a i l e d sp e c if ic a t io n s . func tiona l bl ock dia g r a m comparator and ck q d g q d q d flop latch clock in one shot c os 5v c int r in integrator hl 1ma ?v s v in 00798-001 fi g u r e 1 .
ad652 rev. c | page 2 of 28 table of contents specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 definitions of specifications ....................................................... 5 theory of operation ........................................................................ 6 overrange ...................................................................................... 8 svfc connection for dual supply, positive input voltages .. 9 svfc connections for negative input voltages ...................... 9 svfc connection for bipolar input voltages ........................ 10 plcc connections..................................................................... 11 gain and offset calibration...................................................... 11 gain performance ...................................................................... 12 reference noise .......................................................................... 12 digital interfacing considerations........................................... 12 component selection ................................................................ 12 digital ground............................................................................ 13 single-supply operation ........................................................... 14 frequency-to-voltage converter ............................................. 15 decoupling and grounding...................................................... 16 frequency output multiplier.................................................... 17 single-line multiplexed data transmission .......................... 18 isolated front end...................................................................... 22 a-to-d conversion .................................................................... 22 delta modulator ......................................................................... 23 bridge transducer interface...................................................... 24 outline dimensions ....................................................................... 25 ordering guide............................................................................... 26 revision history 5/04data sheet changed from rev. b to rev. c updated format..............................................................universal changes to gain and offset calibration section.................... 11 updated outline dimensions ................................................... 25 changes to ordering guide ...................................................... 26 2/00data sheet changed from rev. a to rev. b
ad652 rev. c | page 3 of 28 specifications typical @ t a = 25c, v s = 15 v, unless otherwise noted. specifications in boldface are 100% tested at final test and are used to measure outgoing quality levels. table 1. ad652jp/aq/sq ad652kp/bq parameter min typ max min typ max unit voltage-to-frequency mode gain error f clock = 200 khz 0.5 1 0.25 0.5 % f clock = 1 mhz 0.5 1 0.25 0.5 % f clock = 4 mhz 0.5 1.5 0.25 0.75 % gain temperature coefficient f clock = 200 khz 25 50 15 25 ppm/c f clock = 1 mhz 25 50 15 25 ppm/c 10 50 10 30 ppm/c 1 f clock = 4 mhz 25 75 15 50 ppm/c power supply rejection ratio 0.001 0.01 0.001 0.01 %/v linearity error f clock = 200 khz 0.002 0.02 0.002 0.005 % f clock = 1 mhz 0.002 0.02 0.002 0.005 % f clock = 2 mhz 0.01 0.02 0.002 0.005 % f clock = 4 mhz 0.02 0.05 0.01 0.02 % offset (transfer function, rti) 1 3 1 2 mv offset temperature coefficient 10 50 10 25 v/c response time one period of new output frequency plus one clock period. frequency-to-voltage mode gain error, f in = 100 khz fs 0.5 1 0.25 0.5 % linearity error, f in = 100 khz fs 0.002 0.02 0.002 0.01 % input resistors cerdip (figure 2)(0 to 10 v fs range) 19.8 20 20.2 19.8 20 20.2 k? plcc (figure 3) pin 8 to pin 7 9.9 10 10.1 9.9 10 10.1 k? pin 7 to pin 5 (0 v to 5 v fs range) 9.9 10 10.1 9.9 10 10.1 k? pin 8 to pin 5 (0 v to 10 v fs range) 19.8 20 20.2 19.8 20 20.2 k? pin 9 to pin 5 (0 v to 8 v fs range) 15.8 16 16.2 15.8 16 16.2 k? pin 10 to pin 5 (auxiliary input) 19.8 20 20.2 19.8 20 20.2 k? temperature coefficient (all) 50 100 50 100 ppm/c integrator op amp input bias current inverting input (pin 5) 5 20 5 20 na noninverting input (pin 6) 20 50 20 50 na input offset current 20 70 20 70 na input offset current drift 1 3 1 2 na/c input offset voltage 1 3 1 2 mv input offset voltage drift 10 25 10 15 v/c open-loop gain 86 86 db common-mode input range Cv s + 5 +v s C 5 Cv s + 5 +v s C 5 v cmrr 80 80 db bandwidth 14 95 14 95 mhz output voltage range ?1 (+v s ? 4) ?1 (+v s ? 4) v (referred to pin 6, r1 > = 5 k?)
ad652 rev. c | page 4 of 28 ad652jp/aq/sq ad652kp/bq parameter min typ max min typ max unit comparator input bias current 0.5 5 0.5 5 a common-mode voltage ?v s + 4 + v s ? 4 ?v s + 4 +v s ? 4 v clock input maximum frequency 4 5 4 5 mhz threshold voltage (referred to pin 12) 1.2 1.2 v t min to t max 0.8 2.0 0.8 2.0 v input current (?v s < v clk < +v s ) 5 20 5 20 a voltage range ?v s +v s ?v s +v s v rise time 2 2 s output stage v ol (i out = 10 ma) 0.4 0.4 v i ol v ol < 0.8 v 15 15 ma v ol < 0.4 v, t min to t max 8 8 ma i oh (off leakage) 0.01 10 0.01 10 a delay time, positive clock edge to output pulse 150 200 250 150 200 250 ns fall time (load = 500 pf and i sink = 5 ma) 100 100 ns output capacitance 5 5 pf output one-shot pulse width, t os c os = 300 pf 1 1.5 2 1 1.5 2 s c os = 1000 pf 4 5 6 4 5 6 s reference output voltage 4.950 5.0 5.050 4.975 5.0 5.025 v drift 100 50 ppm/c output current source t min to t max 10 10 ma sink 100 500 100 500 a power supply rejection supply range = 12.5 v to 17.5 v 0.015 0.015 %/v output impedance (sourcing current) 0.3 2 0.3 2 ? power supply rated voltage 15 15 v operating range dual supply 6 15 18 6 15 18 v single supply (?v s = 0) +12 +36 +12 +36 v quiescent current 11 15 11 15 ma digital common ?v s +v s ? 4 Cv s +v s ? 4 v analog common ?v s +v s ?v s +v s v temperature range specified performance jp, kp grade 0 +70 0 +70 c aq, bq grade ?40 +85 ?40 +85 c sq grade ?55 +125 c 1 referred to internal v ref . in plcc package, tested on 10 v input range only.
ad652 r e v. c | pa ge 5 o f 2 8 absolute maximum ra tings table 2. p a r a me t e r r a t i n g s t o tal sup p ly v o ltage +v s to ?v s 36 v m a ximum i n put v o ltage (f igur e 6) 36 v m a x imum o utput c u rr en t ( o pen c o llec t or o utput) 50 ma amplifier shor t- cir c uit to gr oun d i n definite stor age t e mpera tur e r a nge: cerdip ?65c to +150c stor age t e mpera tur e r a nge: pl c c ?65c to +150c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd c a ution esd (elec t r o sta t i c dischar g e) sensitiv e devic e . ele c tr os ta tic char g e s as high as 4000 v r e adily ac cumula te on the human body and t e st eq uipmen t and can dischar g e wi thout det e c t ion. although this pr odu c t f e a tur es pr o p r i etar y esd pr otec tio n cir c u i tr y , per m anen t damage ma y oc cur on devic e s subjec ted to high ener gy elec tr o s ta tic dischar g es . ther ef o r e , p r ope r esd pr ecaution s ar e r e c o mmended to a v oid per f or m a nc e degrada t ion or l o ss of func tiona l it y . defi ni tio n s of s p ecifi c a t io ns gain error the ga i n o f a v o l t a g e - t o -f r e q u e n c y co n v er t e r is t h e s c ale fac t o r s e t t i n g t h a t p r o v ides t h e n o minal co n v ersion r e la t i on s h i p , e . g . , 1 mh z f u l l s c ale . the ga i n er r o r is t h e dif f er e n ce in s l op e b e tw e e n t h e ac t u a l an d i d e a l t r an sfer f u n c t i o n s fo r t h e v - f co n v er t e r . linearity error the li n e a r i t y er r o r o f a v - f is t h e de v i a t io n o f t h e ac t u al tra n sf e r fun c ti o n f r o m a s t ra i g h t li n e pa s s i n g t h r o ugh th e end p o i n t s o f t h e t r a n sfer f u n c t i o n . gain te mperat ure coefficient the ga i n t e m p e r a t ur e co ef f i cie n t is t h e ra t e o f cha n g e i n f u l l - s c ale f r e q uen c y as a f u n c t i o n o f t h e tem p era t ur e f r o m +25c t o t min or t max . table 3. pin con f iguration s p i n no . q - 16 p a ck age p - 20a p a ck age 1 + v s nc 2 t r i m +v s 3 t r i m n c 4 op amp out op amp out 5 op amp ? op amp ? 6 op amp + op amp + 7 10 vol t inpu t 5 vol t inpu t 8 ? v s 10 vol t inpu t 9 c os 8 vol t inpu t 10 cl ock input optional 10 v i n put 1 1 f r e q o u t ?v s 1 2 d i g i t a l g n d c os 13 anal og gnd cl ock input 1 4 c o m p ? f r e q o u t 1 5 c o m p + digit a l g n d 16 c o mp ref anal og gnd 1 7 c o m p ? 1 8 c o m p + 1 9 n c 2 0 c o m p r e f
ad652 r e v. c | pa ge 6 o f 2 8 theor y of opera tion a sy n c hr on o u s vfc is simil a r to o t h e r v o l t a g e - t o -f r e q u en c y c o n v e r te rs i n t h a t a n i n te g r a t or i s u s e d to p e r f or m a ch arge - b a lan c e o f t h e i n p u t sig n al w i t h a n i n t e r n al r e fer e n c e c u r r en t. h o w e v e r , ra th e r th a n usi n g a o n e - sh o t as th e p r i m a r y ti m i n g e l emen t, w h ich r e q u ir es a hig h q u a l i t y an d lo w dr if t ca p a c i t o r , a s y nc h r onou s vo lt age - to - f re qu e n c y c o n v e r te r ( s v f c ) u s e s an e x te r n a l cl o c k . th i s a l l o w s t h e de s i g n e r to de te r m i n e t h e s y ste m st a b i l i t y a nd dr i f t b a s e d u p on t h e ex ter n a l clo c k s e le c t e d . a cr ys tal os cil l a t or ma y als o be us ed if desir e d. t h e sv fc a r c h i t ect u r e p r o v i d es o t h e r s y s t em ad v a n t a g e s besides lo w dr if t. i f th e o u t p u t f r e q uen c y is m e as ur e d b y co un t i n g p u ls es ga te d to a sig n a l t h a t is der i ve d f r o m t h e clo c k, t h e clo c k st ab i l i t y is unim p o r t an t and t h e d e v i c e sim p ly pe rf o r m s a s a v o l t a g e - co n t r o ll ed f r eq ue n c y d i vi d e r , p r od uci n g a hig h r e s o l u tion a/d . i f a la rg e n u m b er o f in p u ts m u s t be mon i tore d s i m u l t ane o u sly in a s y ste m , t h e c o n t rol l e d t i ming r e la t i on s h i p b e t w e e n t h e f r e q ue n c y o u t p u t p u ls es a nd t h e us er - su p p lie d clo c k g r e a t l y sim p lif i es t h is sig n a l acq u isi t io n. a l s o , if t h e cl o c k s i g n a l i s prov i d e d by a v f c , t h e output f r e q u e nc y of t h e s v f c i s prop or t i on a l to t h e pro d u c t of t h e t w o i n put v o l t a g es. th er efo r e , m u l t i p lic a t i o n an d a - t o -d co n v ersio n on tw o sig n als a r e p e r f o r m e d sim u l t an e o us l y . 00798-002 +v s 1 trim 2 trim 3 op amp out 4 op amp "? " 5 op amp "+" 6 10 volt input 7 ?v s 8 comp ref 16 comp "+" 15 comp "?" 14 analog gnd 13 digital gnd 12 freq out 11 clock input 10 c os 9 one shot and "d" flop qc k d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference f i gure 2. cerdip p i n c o nf igur ation the p i n o u t s o f th e ad652 svf c a r e sh o w n in f i gur e 2 a nd f i gur e 3. a b l o c k d i a g ram o f t h e de vic e co nf igu r e d as an svfc, a l ong w i t h v a r i ou s s y ste m w a v e f o r m s , i s show n i n fi g u re 4 . 00798-003 op amp ou t 4 op amp "?" 5 op amp "+" 6 5v input 7 10v input 8 comp "+" 18 comp "?" 17 analog gnd 16 digital gnd 15 freq out 14 8v input 9 optional 10v in pu t 10 ?v s 11 c os 12 clock input 13 nc 3 +v s 2 nc 1 comp re f 20 nc 19 1ma 5v reference nc = no connect and "d" flop q ck d q one shot 10k ? 10k ? 16k ? 4k ? ad652 synchronous voltage-to-frequency converter f i g u re 3. pl c c p i n conf ig ur at i o n f i g u re 4 show s t h e t y pi c a l up - a n d - d o w n r a m p i n t e g r a t or output of a ch ar ge - b a l a n c e v f c . a f te r t h e i n t e g r a t or output h a s cr o s s e d t h e co m p a r a t o r t h r e sh ol d an d t h e ou t p ut o f t h e an d ga t e has g o ne hig h , n o thin g ha p p en s un t i l a nega ti v e edg e o f t h e c l oc k co m e s alo n g t o tra n sf e r th e i n f o rm a t i o n t o th e o u t p u t o f th e d fl o p . a t th i s po i n t , th e c l oc k lev e l i s lo w , so th e la t c h d o es n o t cha n g e st a t e. w h e n t h e clo c k r e t u r n s hig h , t h e la t c h o u t p ut g o es hig h and dr i v es t h e s w i t ch t o r e s e t t h e in t e g r a t o r ; a t t h e s a me t i m e , t h e l a t c h dr i v es t h e and g a t e t o a l o w o u t p u t s t a t e . o n th e v e r y n e xt n e ga ti v e ed ge o f th e c l oc k , t h e lo w o u t p u t s t a t e o f th e an d ga t e i s tra n sf e r r e d t o th e o u t p u t o f th e d fl o p . w h en t h e clo c k r e t u r n s hig h , t h e la t c h o u t p ut go es lo w a n d dr i v es t h e sw i t ch b a ck in t o t h e i n teg r a t e m o de . a t t h e s a me t i me , t h e la t c h dr i v es t h e and ga t e t o a m o de w h er e i t t r u t hf u l l y r e la ys t h e i n fo r m a t ion p r es en t e d t o i t b y t h e co m p a r a t o r . b e ca us e t h e r e s e t p u ls es a p plie d t o t h e in t e g r a t o r a r e exac t l y o n e clo c k p e r i o d lon g , t h e o n l y place w h er e dr if t c a n o c c u r is in a va r i a t ion o f t h e symm et r y o f t h e sw i t chin g sp e e d wi t h te m p e r a t u r e. s i n c e each r e s e t p u ls e is iden tic a l , th e ad652 s v fc p r o d uces a ve r y l i ne ar vol t age - to - f re qu e n c y t r ans f e r rel a t i on. a l s o , b e c a u s e al l r e s e t p u ls es a r e ga t e d b y t h e clo c k, t h er e a r e n o p r ob lem s w i t h d i e l ectri c a b so r p ti o n ca usin g th e d u ra ti o n o f a r e se t p u lse t o be in f l ue n c ed b y th e le n g th o f ti m e sin c e th e la s t r e set .
ad652 r e v. c | pa ge 7 o f 2 8 00798-004 comparator and ck q d g q d q d flop latch clock in one shot c os 5v c int r in integrator hl 1ma ?v s v in t os t os integrator output threshold clock comparator out and out d flop out latch out freq out f i gur e 4 . bl oc k diagr a m and s y st em w a v e f o rm s f i g u re 4 show s t h a t t h e p e r i o d b e t w e e n output pu l s e s i s co n s t r a i n e d t o b e an exac t m u lt i p le o f t h e clo c k p e r i o d . c o n s ider a n i n pu t c u r r en t o f exac t l y o n e q u a r t e r t h e val u e o f t h e r e fer e n c e c u r r en t. i n o r der to achie v e a cha r g e b a lan c e , t h e o u t p u t f r eq uen c y eq uals th e c l o c k f r eq uen c y divide d b y f o ur : one cl o c k p e r i o d f o r re s e t an d t h re e cl o c k p e r i o d s of i n te g r a t e. this is sh o w n i n f i gur e 5. i f t h e in p u t c u r r en t is in cr e a s e d b y a ve r y s m a l l amou n t , t h e output f r e q u e nc y s h ou l d a l s o i n c r e a s e b y a v e r y smal l a m o u n t . i n i t ial l y , h o w e v e r , n o ou t p u t c h a n g e is obs e r v e d fo r a v e r y sma l l in cr e a s e in t h e in pu t c u r r en t. the o u t p u t f r eq uen c y co n t in ues t o r u n a t one q u a r ter o f th e c l o c k, de li v e r i n g an a v era g e o f 250 a t o th e s u mming j u n c tion. s i n c e t h e i n p u t c u r r en t is s l ig h t l y la rg er t h a n t h is, cha r g e acc u m u l a t e s in t h e in teg r a t or a n d t h e s a wt o o th sig n al s t a r ts t o dr if t do wn- w a r d . a s th e i n t e gr a t o r s a w t oo th d r i f t s d o w n , th e c o m p a r a t o r t h r e sh old is cr oss e d e a rlier an d e a rlier in e a ch successi v e c y cle , un t i l f i nal l y , a w h ole c y cle is los t . w h e n t h e c y cle is los t , t h e in teg r a t e phas e las t s fo r tw o p e r i o d s o f t h e clo c k in st e a d o f t h e us ual thr e e p e r i o d s. th us, am on g a lo n g s t r i n g o f di vide-b y- fo urs, a n o c casi o n al divide -b y-t h r e e o c c u rs; t h e a v era g e o f t h e output f r e q u e nc y i s ve r y cl o s e to one q u ar te r of t h e cl o c k , but t h e i n st an t a ne ous f r e q uen c y ca n b e ver y dif f er en t. 00798- 005 integrato r out clock threshold f i gure 5 . integr a t or o u tput fo r i in = 25 0 a b e ca us e o f this, i t is v e r y dif f i c u l t t o obs e r v e the wa v e f o r m o n a n oscillosco pe . duri n g all o f th i s ti m e , th e si gnal a t t h e o u t p u t o f th e i n t e gra t o r i s a sa wt oo th w a v e wi th a n en v e l o p e tha t i s also a s a wt o o t h . s e e f i gur e 6. 200 s/box 100 s/box c int freq out 10 s/box clock in 10 s/box 00798-006 f i gure 6 . integr a t or o u tput fo r i in sl ig h t ly gr e a t e r t h an 25 0 s
ad652 r e v. c | pa ge 8 o f 2 8 a n o t h e r w a y t o v i ew th i s i s tha t th e o u t p u t i s a f r eq ue n c y o f a p p r o x i m a t e l y o n e- q u a r t e r o f th e c l oc k th a t h a s been p h a s e mo d u l a te d. a c o nst a n t f r e q u e n c y c a n b e t h ou g h t of a s a c cum u la ti n g ph a s e lin e a r l y w i th tim e a t a ra t e eq ual t o 2f radian s p e r s e cond . th er efo r e , t h e a v era g e o u t p u t f r e q uen c y , w h ich is slig h t ly in excess o f a qua r t e r o f t h e clo c k, r e q u ir es phas e acc u m u l a t i o n a t a cer t a i n ra t e . h o w e ver , sin c e t h e svfc is r u nnin g a t ex ac tl y o n e-q u a r ter o f th e c l o c k, i t do es n o t acc u m u l a t e e n oug h phas e (s e e f i gur e 7). w h e n t h e dif f er en ce bet w een t h e r e q u i r ed p h a s e (a v e ra g e f r eq ue n c y) a n d th e a c t u al phas e e q uals 2, a s t ep- i n phas e is t a k e n w h er e t h e def i ci t is m a d e u p in s t a n t a n e o u s l y . th e o u t p u t f r eq ue n c y i s th en a s t ea d y ca r r i er tha t has been p h as e m o d u l a t e d b y a s a wt o o t h sig n al (s ee f i gur e 7). th e p e r i o d o f t h e s a w t o o t h phas e m o d u l a t i o n is t h e time r e q u ir e d to acc u m u la t e a 2 dif f er en ce in p h as e betw e e n t h e r e q u ir e d a v e r a g e f r e q uen c y a nd on e qua r t e r o f t h e clo c k f r e q uen c y . th e s a w t o o t h phas e m o d u l a t i on a m pli t ude is 2. 00798-007 time time mod (t) actual phase expected phase phase 2 2 2 phase modulation average carrier frequency v out (t) = cos (2 f ave t + mod (t)) f i g u re 7. p h as e m o dulat i on the r e s u l t o f this syn c hr o n ism is tha t t h e ra t e a t whic h da t a ma y b e ext r ac t e d f r o m t h e s e r i es b i t s t r e a m p r o d uce d b y t h e s v fc is limi te d . the o u t p u t p u ls es a r e ty p i cal l y co un te d d u r i n g a f i xe d g a te i n te r v a l a nd t h e re su lt i s i n te r p re te d a s an a v e r age f r e q u e nc y . t h e re s o lut i on of su ch a me a s u r e m e n t i s d e te r m i n e d b y t h e clo c k f r e q uen c y an d t h e ga t e t i me . f o r exa m ple , if t h e c l o c k f r eq uen c y is 4 mh z and t h e g a t e time is 4 . 096 m s , a maxim u m co un t o f 8,192 is p r o d uced b y a f u l l -s cale f r eq uen c y o f 2 mh z . t h us, th e r e so l u ti o n is 13 b i ts. o v err a nge sin c e e a ch r e s e t p u ls e is o n l y o n e clo c k p e r i o d i n len g t h , t h e f u l l -s cale o u t p u t f r e q uen c y is e q ual t o on e-half th e c l o c k f r eq ue n c y . a t full scal e , th e curr e n t s t ee ri n g swi t c h s p en d s h a l f o f th e tim e o n t h e s u m m i n g j u n c ti o n ; th us, a n i n p u t curr e n t o f 0.5 ma c a n be balan c e d . i n t h e cas e o f an o v erra n g e , th e ou t p u t o f t h e in teg r a t or o p a m p dr if ts in t h e n e g a t i ve dir e c t io n a nd t h e output of t h e c o m p ar a t or re m a i n s h i g h . t h e l o g i c c i rc u i t s sim p ly s e t t le i n to a divide -b y - t w o o f t h e clo c k st a t e.
ad652 r e v. c | pa ge 9 o f 2 8 svfc c o nnec tion for du al suppl y , positive inpu t vol t a g es f i gur e 8 s h o w s th e ad652 co nn ec tion s c h e m e f o r th e t r adi t io na l d u a l su p p ly , p o si t i v e in p u t m o de o f op era t ion. t h e v s ra n g e is f r o m 6 v t o 18 v . w h en +v s is lo w e r tha n 9.0 v , a s sh o w n in f i gur e 8, th r e e a d d i ti o n al co nn ectio n s a r e r e q u i r e d the f i rst co n n e c t i o n is to sh o r t pin 13 to pi n 8 (ana lo g gr o u n d to ? v s ) a n d add a p u ll-u p r e sis t o r t o +v s (as sho w n in f i g u re 2 1 ) . t h e pu l l - u p re s i stor i s d e te r m i n e d by t h e f o l l ow i n g eq ua ti o n : a 500 v 5 2 ? = s pullup v r t h e s e c o n n e c t i ons e n su re prop e r op e r a t i o n of t h e 5 v re f e re n c e. t i e p i n 16 t o p i n 6 (as sh o w n in f i gur e 21) t o en s u r e tha t the i n t e g r a t or output r a m p s d o w n f a r e n ou g h to t r ip t h e co m p a r a t o r . the cerd i p -p ac ka ged ad652 accep t s ei t h er a 0 v t o 10 v o r 0 ma t o 0.5 ma f u l l -s cale in p u t sig n al . the t e m p era t ur e dr if t o f th e ad652 is sp ecif ied f o r a 0 v t o 10 v in p u t ra n g e usin g t h e in t e r n a l 20 k? resist o r . i f a c u r r en t i n p u t is us e d , t h e gain dr if t is deg r ade d b y a maxim u m o f 100 p p m /c (t h e t c o f th e 20 k? r e sis t o r ). i f a n ext e r n al r e sis t o r is co nnec t e d t o p i n 5 t o es tab l ish a dif f er en t i n p u t v o l t a g e ra n g e , dr if t is ind u ce d to t h e ext e n t t h a t t h e e x te r n a l re s i stor s tc d i f f e r s f rom t h e t c of t h e i n te r n a l re s i stor . t h e e x t e r n a l re s i stor u s e d to e s t a bl i s h a d i f f e r e n t i n put v o l t a g e ra n g e sho u ld b e s e le c t e d t o p r o v ide a f u l l -s cale c u r r en t o f 0.5 ma (i .e ., 10 k? f o r 0 v t o 5 v). svfc c o nn ec tions fo r nega tive inpu t vo l t a g e s v o lt age s t h at are n e g a t i ve w i t h re sp e c t to g rou n d m a y b e u s e d as the in p u t t o t h e ad652 svf c . i n this c a s e , p i n 7 is g r o u nded a n d t h e i n p u t vol t a g e is a p plie d t o pin 6 (s e e f i gur e 9). i n t h is m o de , t h e in p u t v o l t a g e c a n g o as lo w as 4 v a b o v e ?v s . i n t h i s co nf igura t io n, t h e in p u t is a hig h im p e dan c e , and o n l y the 20 n a (typ ical) in p u t b i as c u r r en t o f the o p a m p m u s t be s u p p lie d b y th e in p u t sig n al . this is co n t rast ed wi t h t h e m o r e us ual p o si ti v e in p u t v o l t a g e conf igura t io n, w h ic h has a 20 k? in p u t im p e dan c e a n d r e q u ir es 0 . 5 ma f r o m t h e sig n a l s o ur ce . 00798-008 + v s 1 2 3 4 ? + 5 6 7 +v s v in 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference r l 5v clock analog gnd digital gnd freq out c int ?v s f i gure 8 . standar d v/f c o n n ectio n fo r p o si ti v e input v o l t age wi th dua l sup p l y 00798-009 +v s 1 2 3 4 5 6 7 +v s ?v s 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference r l 5v clock analog gnd digital gnd freq out c int ? + v in f i gure 9 . nega ti v e v o l t a g e input
ad652 rev. c | page 10 of 28 00798-010 +v s 1 2 3 4 5 6 7 ?v s 8 16 15 14 13 12 11 10 9 one shot and "d" flop qck d q 1ma 20k ? 20k ? ad652 synchronous voltage-to- frequency converter 5v reference r l 5v clock c os analog gnd digital gnd freq out c int v in 5v figure 10. bipolar offset svfc connection for bipolar input voltages a bipolar input voltage of 5 v can be accommodated by injecting a 250 a current into pin 5 (see figure 10). a ?5 v signal provides a zero sum current at the integrator summing junction, which results in a zero-output frequency; a +5 v signal provides a 0.5 ma (full-scale) sum current, which results in the full-scale output frequency. using an external resistor to inject the offset current has some effect on the bipolar offset temperature coefficient. the ideal transfer curve with bipolar inputs is shown in figure 11. the user actually has four options to use in injecting the bipolar offset current into the inverting input of the op amp: 1. use an external resistor for r os and the internal 20 k? resistor for r in (as shown in figure 10). 2. use the internal 20 k? resistor as r os and an external r in . 3. use two external resistors. 4. use two internal resistors for r in and r os (available on plcc version only). option 4 provides the closest to the ideal transfer function as diagrammed in figure 11. figure 12 shows the effects of the transfer relation on the other three options. in the first case, the slope of the transfer function is unchanged with temperature. however, v zero (the input voltage required to produce an output frequency of 0 hz) and f zero (the output frequency when v in = 0 v) changes as the transfer function is displaced parallel to the voltage axis with temperature. in the second case, f zero remains constant, but v zero changes as the transfer function rotates about f zero with temperature changes. in the third case, with two external resistors, the v zero point remains invariant while the slope and offset of the transfer function change with temperature. if selecting this third option, the user should select low drift, matched resistors. 00798-011 v ref v in r os r in ideal transfer relation v zero f out f zero ?5v +5v v in figure 11. ideal bipolar input transfer curve over temperature 00798-012 ideal f out f zero v in temperature perturbed transfer v zero ?5v case 1 r in internal r os external ideal f out f zero v in temperature perturbed v zero ?5v case 2 r in external r os internal ideal f out f zero v in temperature perturbed v zero ?5v case 3 r in external r os external figure 12. actual bipolar input transfer over temperature
ad652 rev. c | page 11 of 28 00798-013 nc = no connect 5 7 8 nc v in + ? nc nc 6 9 10 ad652 synchronous voltage-to- frequency converter 10k ? 10k ? 16k ? 4k ? a. plcc 0v to 10v input 5 7 8 nc nc nc 6 9 10 ad652 synchronous voltage-to- frequency converter 10k ? 10k ? 16k ? 4k ? b. plcc 0v to 8v input v in + ? 5 7 8 nc nc nc 6 9 10 ad652 synchronous voltage-to- frequency converter 10k ? 10k ? 16k ? 4k ? c. plcc 0v to 5v input v in + ? 5 7 8 nc v in 5v nc 6 9 10 ad652 synchronous voltage-to- frequency converter 10k ? 10k ? 16k ? 4k ? d. plcc 5v input 5v ref 20 f i g u re 13. p l cc co n n e c t i o n s the p l cc p a c k a g ed ad652 o f fers addi tional in p u t r e sis t o r s no t fo un d on t h e c e rd ip -p acka g e d de vi ce . th es e r e sis t o r s p r o v ide t h e us er wi t h addi t i o n al in p u t vol t a g e ra n g es. b e sides t h e 10 v ra n g e a v a i lab l e usin g t h e on-chi p r e sis t o r in t h e cerd ip t h e p l cc als o o f f e rs 8 v a n d 5 v ran g es. f i gur e 13a t o f i gur e 13c s h o w t h e p r o p e r co nn e c t i on s fo r t h es e ra n g es w i t h p o si t i v e in p u t v o l t a g es. f o r n e ga t i v e i n pu t v o l t a g es, t h e a p p r o p r i a t e re s i stor shou l d b e t i e d to an a l o g g rou nd a n d t h e i n put vo lt ag e s h o u ld b e a p p l ied t o p i n 6, th e + in p u t o f t h e op a m p . b i p o la r in p u t vol t a g es can be acco mm o d a t e d b y in jec t in g 250 a in t o p i n 5 wi t h t h e us e o f th e 5 v r e f e r e n c e an d t h e i n put re s i stor s . f o r t h e 5 v or 2 . 5 v r a nge, t h e re f e re nc e o u t p u t , p i n 20, sh o u ld be tied t o p i n 10. th e in p u t sig n al sh o u ld th en b e a p p l ied t o p i n 8 f o r a 5 v sig n al a n d t o p i n 7 f o r a 2.5 v sig n al. th e i n p u t co nn e c t i o n s fo r a 5 v ra n g e a r e s h o w n i n fi g u r e 1 3 d . fo r a 4 v r a n g e , t h e i n p u t s i g n a l s h o u l d b e a p pl ie d to pi n 9 , and pi n 2 0 shou l d b e c o n n e c te d to pin 8 . gain a n d o ffse t c a libr a t ion the ga in er r o r o f th e ad652 is las e r tr imm e d to wi thin 0.5 %. i f hig h er acc u rac y is r e q u ir ed , th e in t e r n al 20 k? r e sis t o r m u s t be sh un t e d wi th a 2 m? r e sis t o r t o p r o d uce a p a ral l e l eq ui valen t tha t is 1 % lo w e r in val u e than t h e n o minal 20 k?. f u l l -s cale ad j u s t m e n t is t h en accom p lish e d usin g a 500 ? s e r i es tr imm e r . s e e f i gur e 14 and f i gur e 15. w h en n e ga ti v e in p u t v o l t a g es a r e us ed , this 500 ? tr imm e r is tie d t o g r o u n d and p i n 6 is t h e i n pu t pi n . 00798-014 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference v in +v s 0.02 f 2m ? 500 ? 250k ? 20k ? f i g u re 14. ce r d ip g a in and o f f s et t r i m 00798-015 4 5 6 7 8 18 17 16 15 14 9 10 11 12 13 3 2 1 20 19 1ma 5v reference ad652 and "d" flop q ck d q one shot 10k ? 10k ? 16k ? 4k ? synchronous voltage-to-frequency converter v in 500 ? 500 ? 2m ? 0.02 f 20k ? 350k ? 3.5mv offset trim f i g u re 15. pl c c g a i n and o f f s et t r im
ad652 rev. c | page 12 of 28 this ga i n t r im sh o u ld b e done wi t h an i n p u t vol t a g e o f 9 v , and th e o u t p u t f r eq uen c y s h o u ld b e ad j u s t ed t o ex ac tl y 45% o f th e c l o c k f r eq uen c y . s i n c e th e devi ce set t les in t o a di vi de-b y-2 m o de fo r a n in p u t o v er ra n g e co n d i t ion, ad j u s t i n g t h e ga in wi t h a 10 v in p u t is im p r ac t i ca l; t h e o u t p u t f r e q uen c y is exac t l y o n e-ha lf t h e c l o c k f r eq uen c y if th e ga in is t o o hig h and do es n o t c h an g e wi t h ad j u s t m e n t un t i l t h e exac t p r o p er s c ale fac t o r w a s achi e v e d . th us, the ga in ad j u s t m e n t sh o u ld b e don e wi th a 9 v in p u t. t h e of f s e t of t h e op am p m a y b e t r i m m e d to z e ro w i t h t h e t r i m s c h e me sh o w n in f i gur e 14 f o r th e ce rd ip p a cka g e an d f i gur e 15 f o r th e p l cc p a cka g e . on e wa y o f tr immin g the of f s e t i s by g round i n g pi n 7 ( 8 ) of t h e c e r d i p ( p lc c ) d e v i c e a n d obs e r v in g t h e w a v e fo r m a t p i n 4. i f t h e o f fs et v o l t a g e o f t h e op am p i s p o s i t i ve, t h e i n t e g r a t or h a s s a t u r a te d an d t h e volt age is a t t h e p o si t i v e ra i l . i f t h e o f fs et v o l t a g e is nega t i v e , t h er e is a smal l ef f e c t i v e in p u t c u r r en t tha t c a us es t h e ad652 t o os cil l a t e; a s a wt o o t h wa vef o r m is obs e r v ed a t p i n 4. th e p o t e n t iom e t e r s h o u ld b e a d j u s t ed un til t h e d o wn w a r d s l o p e o f th i s sa w t oo th becom e s v e r y s l o w , do wn t o a f r eq uen c y o f 1 h z o r les s . i n an a n alog-t o-dig i ta l co n v ersio n a p p l ica t ion, a n e a s i er wa y t o tr im th e o f fs et is t o a p p l y a smal l in p u t v o l t a g e , s u c h as 0.01% o f the f u l l -s cale v o l t a g e , a n d ad j u s t t h e p o t e n t iom e t e r un til t h e co r r ec t d i g i t a l output i s re a c he d. gain performance the ad652 ga in er r o r is s p ecif ied as t h e dif f er en c e in s l o p e b e tw e e n t h e ac t u al an d t h e i d e a l t r a n sfer f u n c t i o n o v er t h e f u l l - s c a l e f r e q u e nc y r a nge. f i g u re 1 6 show s a pl ot of t h e t y pi c a l g a i n er r o r cha n g e s v e rs us t h e clo c k i n p u t f r e q ue n c y , n o r m ali z e d t o 100 kh z. f i gur e 16 s h o w s t h e ty p i cal ga in c h a n ges n o r m alize d t o th e o r ig inal 1 00 kh z ga in if , af t e r usin g th e ad652 wi th a f u l l -s cale c l o c k f r eq uen c y o f 100 kh z, th e necess a r y ga tin g tim e is r e d u ced b y incr easin g the c l o c k f r eq uen c y . 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 00798-016 clock frequency (khz) e rror (ppm) 10 3 f i g u re 16. g a in v s . clo c k input reference noise the ad652 has a n o n -bo a r d , p r ecisio n b u f f er ed 5 v r e f e r e n c e a v a i la b l e t o t h e us er . b e sides b e i n g us e d t o o f fs et t h e n o nin- ve r t i n g c o m p ar a t or i n put i n t h e volt age - to - f re qu e n c y mo de, t h i s re f e re nc e c a n b e u s e d f o r ot he r a p pl i c a t i o n s su ch a s of f s e t t i ng th e in p u t t o handle b i p o la r sig n a l s a n d p r o v idi n g b r idge exci t a - tio n . i t can s o urce 10 ma a n d sink 100 a, and is s h o r t-cir c ui t prote c te d. h e av y l o a d i n g of t h e re f e re nc e d o e s not ch ange t h e ga in o f t h e vfc , t h o u g h i t do es a f fe c t t h e ext e r n al r e fer e n c e v o l t a g e . f o r exa m p l e , a 10 ma l o ad in terac t in g wi t h a 0.3 ? typ - ical o u t p u t i m p e dan c e cha n g e s t h e r e fer e n c e v o l t a g e b y 0.06 %. digit a l interf a c ing c o nsider a t ions the ad652 c l o c k in p u t has a hig h im p e dan c e in p u t wi th a t h r e s h old v o l t a g e o f tw o dio d e vol t a g es wi t h r e sp e c t t o dig i t a l grou nd a t pi n 1 2 ( a ppro x i m a tel y 1 . 2 v a t ro om te m p e r atu r e ) . w h en t h e c l o c k in p u t is lo w , 5 a t o 10 a f l o w s o u t o f this p i n. w h en t h e clo c k in p u t is hig h , no c u r r en t f l o w s. the f r eq uen c y o u t p u t is a n op en col l ec t o r p u l l -do w n ca p a b l e o f sinkin g 10 ma wi t h a maxim u m v o l t a g e o f 0.4 v . this dr i v es 6 s t anda r d t t l in p u ts. th e o p en col l ec t o r p u l l -u p v o l t a g e ca n b e a s h i g h a s 3 6 v ab ove d i g i t a l g rou nd. c o mponent selec t ion the ad652 in t e g r a t in g c a p a c i t o r s h o u ld be 0.02 f . i f a la rg e a m o u n t o f n o r m al mo de in t e r f er en ce is exp e c t ed ( m o r e tha n 0.1 v) a n d t h e clo c k f r eq uen c y is les s tha n 500 kh z, an in teg r a t in g c a p a ci t o r o f 0.1 f s h o u ld be us e d . m y la r , p o ly propy l e n e, or p o ly st y r e n e c a p a c i tor s s h ou l d b e u s e d . t h e op e n c o l l e c tor pu l l - u p re s i stor shou l d b e ch o s e n to g i ve adeq u a te l y fas t r i s e tim e s. a t lo w c l o c k f r eq uencies (100 kh z), la rg er r e sis t o r val u es (s e v eral k?) a n d s l o w er ris e t i m e s ma y b e tol e r a te d. h o we ve r , a t hi g h e r cl o c k f r e q u e nc i e s ( 1 m h z) , a l o we r v a lu e re s i stor sh ou l d b e u s e d . t h e l o a d i n g of t h e l o g i c i n put t h at is bein g dr i v en m u s t als o b e ta k e n in t o co n s ider a t io n. f o r exa m ple , if tw o s t anda r d t t l lo ads a r e t o b e dr i v en, a 3.2 ma c u r r en t m u s t be s u n k , lea v in g 6.8 ma f o r th e p u l l -u p r e sis t o r if th e maxim u m lo w leve l v o l t a g e is t o b e ma in ta in e d a t 0.4 v . a 680 ? r e sis t o r w o u l d ther ef o r e be s e lec t ed ((5 v C 0.4 v)/6.8 ma) = 680 ?.
ad652 rev. c | page 13 of 28 the on e- sh o t c a p a ci t o r co n t r o ls t h e p u ls e wi d t h o f t h e f r e q uen c y o u t p u t . th e p u ls e is ini t i a t e d b y t h e r i sin g e d g e o f t h e c l oc k s i gn al . th e d e la y tim e betw ee n t h e ri s i n g ed g e o f th e c l oc k a n d t h e fal l in g e d g e o f th e f r eq u e n c y o u t p u t is typ i cal l y 200 n s . the wid t h o f t h e p u ls e is 5 n s /p f , a n d t h e mi ni m u m wi d t h is a b o u t 200 n s wi th p i n 9 f l o a ting . i f th e on e-sh ot p e r i o d is acciden t al ly ch o s en lo n g er t h an t h e clo c k p e r i o d , t h e wid t h o f t h e p u ls e defa u l ts t o e q ual t h e clo c k p e r i o d . the o n e - sh o t can b e dis a b l e d b y co nn ec tin g p i n 9 t o +v s (f igur e 17); t h e o u t p u t p u lse w i d t h i s t h en eq ual t o t h e c l oc k pe ri od . th e o n e- s h o t i s ac ti va t e d (f igur e 18) b y co nn ec tin g a ca p a c i t o r f r o m p i n 9 t o +v s , ? v s, or d i g i t a l grou n d ( + v s is p r eferr e d). 00798-017 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference +v s f i g u re 17. o n e - s h o t d i s a bl ed 00798-018 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference c os any ac gnd (+v s ,? v s , or digital gnd) f i g u re 18. o n e - s h o t e n abled digit a l ground dig i tal g r o u n d ca n be a t an y p o t e n t ial betw een ?v s and (+v s C 4 v). this ca n be ver y usef u l in sys t em s wi t h der i v e d g r o u n d s ra t h er t h a n s t if f s u p p li es. f o r exa m ple , in a smal l is ola t ed p o w e r c i r c ui t, o f t e n only a sin g le s u p p ly is g e n e ra t e d a n d t h e g r o u nd is s e t b y a divider ta p . s u c h a g r o u n d ca nn ot h a n d le th e la r g e curr e n t s a s socia t e d w i t h d i g i tal s i gn als . w i th th e ad652 svf c , i t is p o s s ib le to co nn ec t the dig i tal g r o u n d t o Cv s f o r a s o lid log i c r e f e r e n c e , as s h own in f i gu r e 19. 00798-019 +v s 1 2 3 4 ? + 5 6 7 v in 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference r l 5v clock freq out c int c os ?v s f i g u re 19. d i g i t a l g nd at ?v s
ad652 rev. c | page 14 of 28 single-sup pl y oper a t ion i n addi tion t o t h e dig i tal g r o u nd bein g conn e c t e d t o Cv s , i t i s als o p o s s i b le t o co nnec t analog g r o u n d t o Cv s o f th e ad652. th us, t h e de vic e is t r u l y o p era t in g f r o m a sin g le -s u p ply v o l t a g e tha t c a n ra n g e f r o m 12 v t o 36 v . this is sh o w n in f i gur e 21 f o r a p o si t i ve volt a g e in p u t, an d in f i gur e 20 fo r a n e g a t i ve vol t a g e in p u t. i n f i gur e 21, the co m p a r a t o r r e f e r e n c e is us ed as a der i v e d g r o u n d ; t h e in p u t v o l t a g e is r e f e r r ed t o this p o in t as we l l as t o th e o p am p co mm on m o de (p in 6 is tied t o p i n 16). s i n c e t h e in p u t sig n al s o u r ce m u s t dr i v e 0 . 5 ma o f f u l l -s c a le sig n al c u r r en t in t o p i n 7, i t m u s t als o dra w t h e exac t s a m e c u r r en t f r o m t h e i n p u t refer e n c e p o t e n t i a l. this c u r r en t is t h er efo r e prov i d e d by t h e 5 v re f e re nc e. i n s i ng l e - s upply op e r a t i o n , an e x te r n a l re s i stor , r pul l up , i s ne c e ss ar y b e t w e e n t h e p o we r supply , + v s , a n d t h e 5 v r e fer e nce output . t h i s re s i stor s h ou l d b e s e l e c t e d su ch t h a t a c u r r e n t of a p p r o x ima t e l y 500 a f l o w s d u rin g o p er a t io n. f o r exa m p l e , wi t h a p o w e r s u p p l y v o l t a g e o f +15 v , a 20 k? r e sis t o r is s e lec t e d ((15 v C 5 v)/500 a = 20 k?). f i g u re 2 0 show s t h e ne g a t i v e vo lt age i n put c o n f i g u r a t i o n f o r usin g t h e ad65 2 in sin g le -su p ply m o de . i n t h is m o d e , t h e sig n a l s o u r c e i s d r iv i n g t h e + i n put of t h e op a m p , w h i c h re qu i r e s on ly 20 na (typ ical) co m p a r ed t o the 0. 5 m a r e q u i r ed in th e pos i ti v e in p u t v o l t a g e conf igura t io n. the v o l t a g e a t pi n 6 ma y go as lo w as 4 v a b o v e g r o u n d (?v s p i n 8). sin c e t h e i n pu t r e fer e n c e is 5 . 0 v a b o v e g r o u nd, t h is le a v es a 1 v wi ndo w fo r t h e i n p u t sig n al. t o dr i v e t h e in teg r a t ing c a p a ci to r wi t h a 0.5 ma f u l l -s cale c u r r en t, i t is nec e s s a r y t o p r o v ide a n ext e r n al 2 k? r e sis t o r . this r e s u l t s in a 2 k? r e sis t o r a n d a 1 v in p u t ra n g e. th e ext e r n al 2 k? r e sis t o r s h o u ld be a lo w tc m e tal-f i l m ty p e f o r lo w e s t dr if t deg r a d a t ion. 00798-021 +v s 1 2 3 4 ? + 5 6 7 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? 2k ? ad652 synchronous voltage-to- frequency converter 5v reference r l 5v clock analog gnd digital gnd c os c int signal source 1v full scale input reference r pullup f i gure 20. sing le-s up ply m o de negat i v e v o lt age input 00798-020 +v s 1 2 3 4 ? + 5 6 7 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference r l 5v clock analog gnd digital gnd freq out c os c int signal source analog gnd i signal 0.5ma full scale input reference r pullup i signal f i gure 21. sing le-s up ply m o de p o sitive v o ltage input
ad652 rev. c | page 15 of 28 frequenc y - t o - v ol t a g e c o nverte r the ad652 svfc als o w o rks as a f r eq uen c y-t o -v ol ta g e c o n v e r te r . f i g u re 2 2 show s t h e c o n n e c t i on d i ag r a m f o r f / v co n v ersio n . i n t h is cas e , th e nega ti v e in p u t o f the co m p a r a t o r is fe d t h e in p u t p u ls es. ei t h er com p a r a t o r in pu t ma y b e us e d s o t h a t an i n p u t p u ls e o f ei t h er p o l a r i ty ma y b e a pplie d t o t h e f/ v . i n f i gur e 22, the + in p u t is tied t o a 1.2 v r e f e r e n c e an d lo w- lev e l t t l p u lses a r e used a s t h e f r eq ue n c y i n p u t . th e p u lse m u s t be lo w o n th e fallin g ed ge o f th e c l oc k . o n th e s u b s e q ue n t r i sin g edg e , the 1 ma c u r r en t s o ur ce is swi t ch e d t o the in teg r a t o r su m m in g j u n c t i on and ra m p s u p t h e v o l t a g e a t pi n 4. d u e t o t h e ac t i on o f t h e and g a t e , t h e 1 ma c u r r en t is sw i t ch e d o f f a f t e r o n ly o n e clo c k p e r i o d . the a v er a g e c u r r en t de l i v e r e d to th e s u mmin g j u n c tion va r i es f r o m 0 ma t o 0.5 ma; usin g t h e in t e r n a l 20 k? resist o r , t h is r e su l t s in a f u l l -s c a le o u t p ut v o l t a g e o f 10 v a t p i n 4. t h e f r e q u e nc y re sp ons e of t h e c i rc u i t i s d e te r m i n e d by t h e ca p a c i t o r ; th e ? 3 db f r eq uen c y is sim p l y th e rc tim e co ns tan t . a tradeo f f exis ts betw een r i p p l e a n d r e s p on s e . i f lo w r i p p le is desir e d , a l a rg e val u e c a p a ci t o r m u s t be us e d (1 f); if fas t r e s p o n s e is n e e d ed , a smal l ca p a ci t o r is us ed (1 nf minim u m). the o p a m p can dr i v e a 5 k? r e sis t o r lo ad t o 10 v , usin g a 15 v pos i ti v e po w e r s u p p l y . i f a l a r g e l o a d c a pa ci ta n c e ( 0 . 0 1 f ) m u s t b e dr i v en, i t is ne ces s a r y t o is ola t e t h e lo ad wi t h a 50 ? r e sis t o r as sh o w n. b e c a us e th e 50 ? r e sis t o r is 0.25% of th e f u l l s c ale , a n d t h e sp e c if ie d ga in er r o r w i t h t h e 20 k? r e sist o r is 0.5%, t h is e x t r a re s i stor on ly i n c r e a s e s t h e tot a l g a i n e r ror to 0 . 7 5 % m a x . the cir c ui t sh own is uni p ola r and o n l y a 0 v t o +10 v o u t p u t is a l l o we d. t h e i n t e g r a t or op a m p i s not a ge ne r a l - pu r p o s e op a m p . i n s t ead , i t has b e en o p timize d f o r sim p lici ty a n d hig h sp e e d . th e m o st sig n if ican t d i f f er en ce b e tw e e n t h is a m plif ier an d a ge ne r a l - pu r p o s e op am p i s t h e l a ck of a n i n t e g r a t or ( o r l e vel s h i f t ) st age . c o n s e q uen t ly , t h e v o l t a g e on t h e o u t p ut (p in 4) m u s t alw a ys b e m o r e po s i ti v e th a n 1 v b e l o w th e i n p u t s ( p i n s 6 a n d 7 ) . f o r exa m ple , in t h e f - t o -v con v ersio n m o de , t h e no ni n v er t i n g i n pu t of t h e op am p ( p i n 6 ) i s g rou nd e d , w h i c h me a n s t h e output (p in 4) ca nn ot g o be lo w ?1 v . n o r m al o p era t ion o f th e cir c ui t as show n ne ve r c a l l s for a ne g a t i ve volt age a t t h e out p ut . a s e con d dif f er en c e b e tw e e n t h is o p a m p and a g e n e ral- p u r p os e a m p l i f i e r i s th a t th e o u t p u t o n l y s i nk s 1. 5 m a t o th e n e ga ti v e supply . t h e on l y pu l l - d ow n ot h e r t h an t h e 1 m a c u r r e n t u s e d f o r v o l t a g e-t o -f r e q u en c y con v ersio n is a 0.5 ma s o ur ce . the o p a m p s o ur ces a g r e a t de al o f c u r r en t f r o m t h e p o si t i v e s u p p ly , an d i s i n te r n a l ly prote c te d by c u r r e n t l i m i t i ng . t h e op a m p o u t p ut ma y b e dr i v en t o wi t h in 4 v o f t h e p o si t i v e s u p p ly w h e n n o t s o ur ci n g exter n al c u r r en t. w h en s o ur cing 10 ma, t h e o u t - p u t v o l t a g e ma y b e dr i v e n t o wi t h in 6 v o f t h e p o si t i v e s u p p ly . 00798-022 clock freq in volts out loads on falling edge of ck shifts out on rising edge of cl frequency to volts converter +v s ?v s 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? 50 ? 0.01 f 5k ? 5k ? ad652 synchronous voltage-to- frequency converter 5v reference clock 5v freq in digital gnd c nc nc 1n4148 ? + v out fi g u r e 2 2 . fr e q u e n c y - t o - v o l t a g e c o n v e r t e r
ad652 rev. c | page 16 of 28 decoupling and grounding it is good engineering practice to use bypass capacitors on the supply-voltage pins, and to insert small valued resistors (10 ? to 100 ?) in the supply lines to provide a measure of decoupling between the various circuits in a system. ceramic capacitors of 0.1 f to 1.0 f should be applied between the supply voltage pins and analog signal ground for proper bypassing on the ad652. additionally, a larger board-level decoupling capacitor of 1 f to 10 f should be located relatively close to the ad652 on each power supply line. such precautions are imperative in high resolution data acquisition applications where one expects to exploit the full linearity and dynamic range of the ad652. separate digital and analog grounds are provided on the ad652. only the emitter of the open-collector frequency output transistor and the clock input threshold are returned to the digital ground. only the 5 v reference is connected to analog ground. the purpose of the two separate grounds is to allow isolation between the high precision analog signals and the digital section of the circuitry. much noise can be tolerated on the digital ground without affecting the accuracy of the vfc. such ground noise is inevitable when switching the large currents associated with the frequency output signal. at high full-scale frequencies, it is necessary to use a pull-up resistor of about 500 ? in order to get the rise time fast enough to provide well-defined output pulses. this means that from a 5 v logic supply, for example, the open collector output draws 10 ma. this much current being switched causes ringing on long ground runs due to the self-inductance of the wires. for instance, 20-gauge wire has an inductance of about 20 nh per inch; a current of 10 ma being switched in 50 ns at the end of 12 inches of 20-gauge wire produces a voltage spike of 50 mv. the separate digital ground of the ad652 easily handles these types of switching transients. a problem remains from interference caused by radiation of electromagnetic energy from these fast transients. typically, a voltage spike is produced by inductive switching transients; these spikes can capacitively couple into other sections of the circuit. another problem is ringing of ground lines and power supply lines due to the distributed capacitance and inductance of the wires. such ringing can also couple interference into sensitive analog circuits. the best solution to these problems is proper bypassing of the logic supply at the ad652 package. a 1 f to 10 f tantalum capacitor should be connected directly to the supply side of the pull-up resistor and to the digital ground, pin 12. the pull-up resistor should be connected directly to the frequency output, pin 11. the lead lengths on the bypass capacitor and the pull-up resistor should be as short as possible. the capacitor supplies (or absorbs) the current transients, and large ac signals flow in a physically small loop through the capacitor, pull-up resistor, and frequency output transistor. it is important that the loop be physically small for two reasons: first, there is less inductance if the wires are short, and second, the loop does not radiate rfi efficiently. the digital ground (pin 12) should be separately connected to the power supply ground. note that the leads to the digital power supply are only carrying dc current. there may be a dc ground drop due to the difference in currents returned on the analog and digital grounds. this does not cause a problem; these features greatly ease power distribution and ground manage-ment in large systems. the proper technique for grounding requires separate digital and analog ground returns to the power supply. also, the signal ground must be referred directly to the analog ground (pin 6) at the package. more information on proper grounding and reduction of interference can be found in noise reduction techniques in electronic systems , by h.w. ort, (john wiley, 1976).
ad652 rev. c | page 17 of 28 00798-023 +15v 1 2 3 4 5 6 7 200pf ?15v 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference +5v 0.02 f ? + v2 0v?10v f out f c +15v 1 2 3 4 5 6 7 ?15v 8 16 15 14 13 12 11 10 9 one shot and "d" flop qc k d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference 400pf v out 2k ? +5v 1mhz clock input 4 3 osc/driver a b 74ls86 c 6 5 8 1 2 7 c t 200pf c1 500pf 1k ? r pu 2.87k ? r t 1k ? r3 1k ? r2 2k ? r1 8.06k ? v1 0v?10v +5v ad654 fi g u r e 2 3 . fr e q u e n c y o u t p u t m u l t i p l i e r frequenc y output m u l t iplier the ad652 can s e r v e as a f r eq uen c y o u t p u t m u l t i p lier w h en us ed in co n j u n c t io n wi t h a standa r d v o l t a g e-t o -f r e q u en c y co n v er t e r . f i gur e 23 s h o w s t h e l o w cos t ad654 vfc bein g us e d as the c l o c k in p u t t o the ad652 . als o s h o w n is a s e cond ad65 2 in t h e f/v m o de . the ad654 is s e t u p t o p r o d u c e a n o u t p u t f r eq uen c y o f 0 kh z t o 500 kh z f o r a n in p u t v o l t a g e (v 1 ) ra n g e o f 0 v t o 10 v . th e us e o f r4, c1 , a n d t h e x o r ga t e do ub les t h is o u t p u t f r eq uen c y f r o m 0 kh zC5 00 kh z t o 0 m h zC1 mh z. this 1 mhz f u l l - s c a l e f r e q ue n c y is t h en us e d a s t h e clo c k in p u t t o th e ad652 s v fc. b e ca us e th e ad652 f u l l -s cale o u t p u t f r e q uen c y is o n e-half t h e clo c k f r e q uen c y , t h e 1 mh z fs clo c k f r eq uen c y es ta blis h e s a 500 kh z maxim u m o u t p u t f r eq uen c y f o r th e ad652 w h en i t s in p u t v o l t ag e (v 2 ) is 10 v . the us er t h er e - f o r e has a n o u t p u t f r eq uen c y ra n g e f r o m 0 kh z t o 500 kh z, w h i c h i s prop or t i on a l to t h e pro d u c t of v 1 an d v 2 .
ad652 rev. c | page 18 of 28 this can be sh own in eq u a tion f o r m , wh er e f c is th e ad654 output f r e q u e nc y and f ou t is t h e ad652 o u t p u t f r eq uen c y : v 10 mhz 1 1 c v f = ? ? ? ? ? ? ? ? ? ? ? ? = v 10 2 c 2 out f v f () () ? ? ? ? ? ? ? ? = v 10 v 10 2 mhz 1 2 1 out v v f f ou t = v 1 v 2 5 kh z/ v 2 t h e s c op e p h ot o i n f i g u re 2 4 s h ow s v 1 an d v 2 (t o p tw o traces) a n d t h e o u t p u t o f t h e f - v (b ot to m t r ace). v 1 v 2 v out 00798-024 f i g u re 24. m u lt ip l i e r w a vef o rms single-line ml t ipleed d a t a tr ansmission i t i s of te n ne c e s s ar y to me asu r e s e ve r a l d i f f e r e n t s i g n a l s and rel a y t h e i n f o r m a t i o n to s o me re mot e l o c a t i on u s i n g a m i n i - m u m am o u n t of ca b l e . m u l t i p le ad652 svfc devices ma y be us e d wi t h a m u lt i p has e clo c k t o co m b i n e t h es e m e as ur e m en ts fo r s e r i al t r a n smis sio n and dem u l t i p lexing. f i gur e 25 s h o w s a b l o c k dia g ra m of a sin g le-lin e m u l t i p lexed da t a t r a n smis sio n sys t em wi th hig h n o is e imm u ni ty . f i gur e 26, f i gur e 27, a n d f i gur e 30 sh o w t h e svfc m u l t i p lexer , a r e p r es en t a t i v e m e a n s of da ta tra n s m i s s i o n , a n d a n s v fc d e m u l t i p le x e r r e s p ecti v e l y . multiplex e r f i gur e 30 sh o w s t h e svfc m u l t i p lexer . th e clo c k in p u ts fo r t h e s e v e ral svfc cha n n e ls a r e g e nera t e d b y a tim 9904a 4-p h as e clo c k dr i v er , a n d t h e f r e q uen c y o u t p u t s a r e com b i n e d b y s t ra p p in g al l t h e f r eq uen c y o u t p u t p i n s t o g e th er (a wir e o r co nnec t io n). the o n e-sh o t in t h e ad652 s e ts t h e p u ls e wid t h o f th e f r eq uen c y o u t p u t p u lses t o be s l igh t l y sh o r ter tha n o n e q u a r t e r o f t h e cl o c k p e r i o d . s y nchr o n iz a t ion is achie v e d b y a p plyi n g on e o f t h e fo ur a v ai la b l e phas es t o a f i xe d t t l on e- s h ot (121) a n d co m b inin g t h e o u t p u t wi th exter n al tra n sis t o r . the wid t h o f t h is syn c p u ls e is sh o r t e r t h a n t h e wi d t h o f t h e f r e q uen c y o u t p u t p u ls es t o faci l i t a t e de co din g t h e sig n al. th e rc l a g ne t w or k on t h e i n put of t h e o n e - s h ot pr ov i d e s a sl i g h t de l a y b e tw e e n t h e r i sin g e d g e of t h e clo c k and t h e s y n c p u ls e in o r der t o ma t c h th e 150 n s dela y o f th e ad652 b e tw een t h e r i sin g edg e o f th e c l o c k an d t h e o u t p u t p u lse . trans m itter th e m u lt i p l e x s i g n a l c a n b e t r an s m i tte d i n an y man n e r su i t abl e to t h e t a s k a t h a n d . a pu l s e t r an s f or me r or an opto - i s o l a tor c a n p r o v ide ga lva n i c is ola t ion; ext r eme l y hig h v o l t a g e is ol a t ion o r t r ans m i s s i on t h rou g h s e ve re r f e n v i ron m e n t s c a n b e a c c o m p - lis h e d wi t h a f i b e r o p tic link; te l e m e tr y can b e ac hiev e d wi t h a radio link. the cir c ui t sh o w n in f i gur e 27 us es a n ei a rs -422 st anda r d fo r dig i t a l da t a t r an sm issio n o v er a b a l a n c e d li ne. f i gur e 24 sh o w s t h e wa v e fo r m s o f t h e fo ur clo c k phas es and t h e m u l t i p lex o u t p u t sig n al. n o t e t h a t t h e sy n c p u ls e is p r es en t e v er y clo c k c y cle , b u t t h e da t a pu ls es a r e n o m o r e f r e q uen t t h a n e v er y o t h e r clo c k c y cle sin c e t h e maxim u m o u t p u t f r e q uen c y f r o m t h e svfc is half t h e clo c k f r e q uen c y . th e clo c k f r e q uen c y us ed in t h is cir c ui t is 819.2 kh z, whic h p r o v ides m o r e than 16 b i ts o f r e s o l u tio n if 100 m s g a t e t i m e is al lo w e d f o r co un tin g p u ls es o f t h e de co de d ou t p u t f r e q uen c ie s. 00798-025 ad652 v in1 ad652 v in2 ad652 v in3 one shot 1 2 3 4 clk generator svfc multiplexer (see figure 26) ad652 2 v out1 ad652 3 v out2 ad652 4 v out3 svfc demux f1 f2 f3 svfc demultiplexer (see figure 30) demultiplexer frequency to voltage conversion (see figure 31) transmission link transmission link (see figure 27) f i gur e 2 5 . si ng le-line mul t i p le x e d da t a t r a n s m i ssio n bloc k dia g r a m
ad652 rev. c | page 19 of 28 00798-026 ?v s v in2 2 +v s 0.02 f 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad652 synchronous voltage-to- frequency converter 15pf ?v s v in3 3 +v s 0.02 f 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad652 synchronous voltage-to- frequency converter 15pf ?v s v in4 4 +v s 0.02 f 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad652 synchronous voltage-to- frequency converter 15pf multiplex out 1 14 2 13 3 12 4 11 5 10 6 9 7 8 qq one shot '121 1 150 ? 1500pf gnd nc r int c ext r ext /c ext nc nc v cc q a2 a1 nc 18pf 10k ? 2n2222 500 ? +5v 2k ? 50pf +5v 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 4 7.4 h l = 41 turns t50 ?7 core micrometals c = 300pf 3 1 +5v +5v 3.2768mhz crystal +5v 2 1k ? tank 1 tim 9904a tank 2 xtal 2 xtal 4 ffq oscin ffd oscout 4 ttl 2 ttl 3 ttl 1 ttl 3v dd 4 1 2 gnd 1 gnd 2 v cc f i g u re 26. sv fc m u lt ipl e x e r 00798-027 input b gnd 75 ? 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 inputs a from encoder mpx input +5v a outputs enable b outputs d outputs c outputs enable inputs d input c 500 feet belden 9272 78 ? shielded pair 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 inputs a +5v mpx output to decoder am26ls33 quad differential line receiver am26ls31 quad high speed differential line receiver output a output c enable inputs c inputs b inputs d enable input d output b f i g u re 27. r s -4 22 s t anda r d d a t a t r an s m is s i on
ad652 rev. c | page 20 of 28 svfc demultiplexer the demultiplexer needed to separate the combined signals is shown in figure 30. a phase-locked loop drives another 4-phase clock chip to lock onto the reconstructed clock signal. the sync pulses are distinguished from the data pulses by their shorter duration. each falling edge on the multiplex input signal triggers the one-shot; at the end of this one-shot pulse, the multiplex input signal is sampled by a d-type flip-flop. if the signal is high, the pulse was short (a sync pulse) and the q output of the d-flop goes low. the d-flop is cleared a short time (two gate delays) later, and the clock is reconstructed as a stream of short, low-going pulses. if the multiplex input is a data pulse, then the signal will still be low and no pulse will appear at the reconstructed clock output when the d-flop samples at the end of the one-shot period. see figure 29. if it is desired to recover the individual frequency signals, the multiplex input is sampled with a d-flop at the appropriate time, as determined by the rising edge of the various phases generated by the clock chip. these frequency signals can be counted as a ratio relative to the reconstructed clock, so it is not even necessary for the transmitter to be crystal-controlled as shown in figure 30. 00798-029 1 1 sync 2 3 data 4 2 3 4 1multiple x output figure 28. multiplexer waveforms 00798-030 multiplex input one shot reconstructed clock 1 (phase locked to reconstructed clock) figure 29. demultiplexer waveforms 00798-028 14 13 5 4 10 4 2 11 8 9 0.1 f phase lock loop mc4044 3 1 3.01k ? 719 ? 1k ? +5v +5v 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 4 3 1 +5v 2 tank 1 tim 9904a 4 phase clock tank 2 xtal 2 xtal 1 ffq oscin ffd oscout 3 v dd 4 1 2 gnd 1 gnd 2 v cc 1 ttl 2 ttl 3 ttl 4 ttl 130 ? 150 ? 3 16 15 11 6 8 9 7 2 4 5 +5v 50pf vco 'ls629 390pf '00 '00 clear q clock d 1/2 '74 reconstructed clock output mpx input 1 14 2 13 3 12 4 11 5 10 6 9 7 8 qq one shot '121 gnd nc r int c ext r ext /c ext nc nc v cc q +5v a2 a1 nc 2k ? 50pf +5v q d clock q f2 2 '74 (1/2) d clock q f3 reconstructed frequency outputs 3 '74 (1/2) d clock q f4 4 '74 (1/2) nc = no connect figure 30. svfc demultiplexers
ad652 rev. c | page 21 of 28 00798-031 ?v s 2 +v s 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad652 synchronous voltage-to- frequency converter 0.02 f v olts out v 2 +5v 4k ? mpx input ?v s 3 +v s 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad652 synchronous voltage-to- frequency converter 0.02 f volts out v 3 ?v s 4 +v s 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad652 synchronous voltage-to- frequency converter 0.02 f volts out v 4 1n4148 2, 3, 4 are pins 15, 7, 6 of tim9904a from demux figure 30 figure 31. demultiplexer frequency-to-voltage conversion 00798-032 +5v transformer pico 31080 24 turns t50- micrometals ck '74 q d ck '74 q d q 500 ? +15v 1 2 3 4 5 6 7 ?15v 8 16 15 14 13 12 11 10 9 one shot and "d" flop qck d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference 0.02 f 1nf lo hi v in 3k ? 1k ? 1nf 6n137 opto- isolator 5 4 6 3 7 2 8 1 isolation barrier frequency output 2n6659 2n6659 mylar 0.01 f +5v 10 h 100 ? 100 ? 12 3 1.65k ? 1.65k ? ad654 1 8 2 7 3 6 4 5 driver osc 200pf 1.2k ? 6.8k ? 10k ? 1.5k ? v ad589 1.2v +5v 1n4148 4 5 6 7 +15v reg 7815 ?15v reg 7915 47 f 47 f 47 f 47 f +15v ?15v 10k ? figure 32. isolated synchronous vfc analog signal reconstruction if it is desired to reconstruct the analog voltages from the multiplex signal, three more ad652 svfc devices are used as frequency-to-voltage converters, as shown in figure 31. the comparator inputs of all the devices are strapped together, the + inputs are held at a 1.2 v ttl threshold, and the ? inputs are driven by the multiplex input. the three clock inputs are driven by the ? outputs of the clock chip. remember that data at the comparator input of the svfc is loaded on the falling edge of the clock signal and shifted out on the next rising edge. note that the frequency signals for each data channel are available at the frequency output pin of each fvc.
ad652 rev. c | page 22 of 28 isolated front end in some applications, it may be necessary to have complete galvanic isolation between the analog signals being measured and the digital portions of the circuit. the circuit shown in figure 32 runs off a single 5 v power supply and provides a self- contained, completely isolated analog measurement system. the power for the ad652 svfc is provided by a chopper and a transformer, and is regulated to 15 v. both the chopper frequency and the ad652 clock frequency are 125 khz, with the clock signal being relayed to the svfc through the transformer. the frequency output signal is relayed through an opto-isolator and latched into a d flop. the chopper frequency is generated from an ad654 vfc, and is frequency divided by two to develop differential drive for the chopper transistors, and to ensure an accurate 50% duty cycle. the pull- up resistors on the d flop outputs provide a well-defined high level voltage to the choppers to equalize the drive in each direction. the 10 h inductor in the 5 v lead of the transformer primary is necessary to equalize any residual imbalance in the drive on each half cycle, and thus prevent saturation of the core. the capacitor across the primary resonates the system so that under light loading conditions on the secondary, the wave shape is sinusoidal and the clock frequency is relayed to the svfc. to adjust the chopper frequency, disconnect any load on the secondary and tune the ad654 for a minimum in the supply current drawn from the 5 v supply. a-to-d conversion in performing an a-to-d conversion, the output pulses of a vfc are counted for a fixed-gate interval. to achieve maximum performance with the ad652, the fixed-gate interval should be generated using a multiple of the svfc clock input. counting in this manner eliminates any errors due to the clock (whether it be jitter, drift with time or temperature, and so on) since it is the ratio of the clock and output frequencies that is being measured. the resolution of the a-to-d conversion measurement is determined by the clock frequency and the gate time. if, for instance, a resolution of 12 bits is desired and the clock frequency is 1 mhz (resulting in an ad652 fs frequency of 500 khz) the gate time is: () ms 192 . 8 sec 10 1 8192 4096 2 mhz 1 2 1 6 1 1 1 C = = ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? n freq clock n freq fs where n is the total number of codes for a given resolution. figure 33 shows the ad652 svfc as an a-to-d converter in block diagram form. 00798-033 v in ad652 counter to p input gate f out clock 2n figure 33. block diagram of svfc a-to-d converter to provide the 2n block, a single-chip counter such as the 4020b can be used. the 4020b is a 14-stage binary ripple counter that has a clock and master reset for inputs, and buffered outputs from the first stage and the last 11 stages. the output of the first stage is f clock 2 1 = f clock /2, while the output of the last stage is f clock 2 14 = f clock /16384. therefore, using this single chip counter as the 2n block, 13-bit resolution can be achieved. higher resolution can be achieved by cascading d- type flip flops or another 4020b with the counter. table 4 shows the relationship between clock frequency and gate time for various degrees of resolution. note that if the variables are chosen such that the gate times are multiples of 50 hz, 60 hz, or 400 hz, normal mode rejection (nmr) of those line frequencies occur. table 4 . resolution n clock conversion or gate time (ms) typical linearity (%) comments 12 bits 4096 81.92 khz 100 0.002 50 hz, 60 hz,400 hz nmr 12 bits 4096 2 mhz 4.096 0.01 12 bits 4096 4 mhz 2.048 0.02 4 digits 10000 200 khz 100 0.002 50 hz, 60 hz, 400 hz nmr 14 bits 16384 327.68 khz 100 0.002 50 hz, 60 hz, 400 hz nmr 14 bits 16384 1.966 mhz 16.66 0.01 60 hz nmr 14 bits 16384 1.638 mhz 20 0.01 50 hz nmr 4? digits 20000 400 khz 100 0.002 50 hz, 60 hz, 400 hz nmr 16 bits 65536 655.36 khz 200 0.002 50 hz, 60 hz, 400 hz nmr 16 bits 65536 4 mhz 32.77 0.02
ad652 rev. c | page 23 of 28 delta modulator the circuit of figure 34 shows the ad652 configured as a delta modulator. a reference voltage is applied to the input of the integrator (pin 7), which sets the steady state output frequency at one-half of the ad652 full-scale frequency (1/4 of the clock frequency). as a 0 v to 10 v input signal is applied to the comparator (pin 15), the output of the integrator attempts to track this signal. for an input in an idling condition (dc), the output frequency is one-half full scale. for positive-going signals, the output frequency is between one-half full scale and full scale; for negative-going signals, the output frequency is between zero and one-half full scale. the output frequency corresponds to the slope of the comparator input signal. 00798-034 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 one shot and "d" flop qck d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference +15v 360pf 0.0047 f ?15v clock v in (0v to 10v ) f out +5v 0.01 f 1k ? figure 34. delta modulator since the output frequency corresponds to the slope of the input signal, the delta modulator acts as a differentiator. a delta modulator is thus a direct way of finding the derivative of a signal. this is useful in systems where, for example, a signal corresponding to velocity exists, and it is desired to determine acceleration. figure 35 is a scope photo showing a 20 khz, 0 v to 10 v sine wave used as the input to the comparator and its ramp-wise approximation at the integrator output. the clock frequency used as 2 mhz and the integrating capacitor was 360 pf. figure 36 shows the same input signal and its ramp-wise approximation, along with the output frequency corresponding to the derivative of the input signal. in this case, the clock frequency was 50 khz. the choice of an integrating capacitor is primarily dictated by the input signal bandwidth. figure 37 shows this relationship. note that as the value of c int is lowered, the ramp size of the integrator approximation becomes larger. this can be compensated for by increasing the clock frequency. the effect of the clock frequency on the ramp size is demonstrated in figure 35 and figure 36. 00798-035 figure 35. delta modulator input signal and ramp-wise approximation 00798-036 figure 36. delta modulator input signal ramp-wise approximation and output frequency 100 1k 10k 100 1k 10k 00798-037 input signal bandwidth (hz) c int (pf) figure 37. maximum integrating cap value vs. input signal bandwidth
ad652 rev. c | page 24 of 28 bridge transducer interface the circuit of figure 38 illustrates a simple interface between the ad652 and a bridge-type transducer. the ad652 is an ideal choice because its buffered 5 v reference can be used as the bridge excitation, thereby ratiometrically eliminating the gain drift related errors. this reference provides a minimum of 10 ma of external current, which is adequate for bridge resistance of 600 ? and above. if, for example, the bridge resistance is 120 ? or 350 ?, an external pull-up resistor ( r pu ) is required. r pu and can be calculated using the following formula: ma 10 v 5 v 5 (max) ? ? + = bridge s pu r v r an instrumentation amplifier is used to condition the bridge signal before presenting it to the svfc. with its high cmrr, the ad652 minimizes common-mode errors and can be set to arbitrary gains between 1 and 10,000 via three resistors, simplifying the scaling for the parts calibrated 10 v input range. these resistors should be selected such that the following equation holds: ? ? ? ? ? ? ? ? + = 1 2 v 10 g f bridge r r v where 10 k? r f 20 k?, and v bridge is the maximum output voltage of the bridge. the bridge output may be unipolar, as is the case for most pressure transducers, or it may be bipolar as in some strain measurements. if the signal is unipolar, the reference input of the ad625 (pin 7) is simply grounded. if the bridge has a bipolar output, however, the ad652 reference can be tied to pin 7, thereby, converting a 5 v signal (after gain) into a 0 v to +10 v input for the svfc. 00798-038 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 one shot and "d" flop qck d q 1ma 20k ? ad652 synchronous voltage-to- frequency converter 5v reference 9 8 11 7 10 1 5 2 15 12 16 ad625 r bridge v bridge + ? r f r g r f +15v ?15v 1 2 s1 +15v clock in freq out +15v v logic r l r pu ?15v c int notes 1. r f should be between 10k ? and 20k ? . 2. r pu needed if r bridge 600 ? 3. s1 in position 1 for unipolar signals and position 2 for bipolar signals. f out =v bridge f clock 2 10v + 1 2r f r g figure 38. bridge transducer interface
ad652 rev. c | page 25 of 28 outline dimensions 16 18 9 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.840 (21.34) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design f i gure 39. 1 6 -l ead cer a m i c d u a l i n -li n e p a ck age [ce r dip ] (q -16) di me nsio ns sho w n i n i n che s a n d ( m il lim e t e r s) 0. 020 ( 0 . 50) r bo t t o m vi ew (p i n s u p ) 0. 02 5 ( 0. 64 ) m i n 0. 02 1 ( 0. 53 ) 0. 01 3 ( 0. 33 ) 0 . 330 ( 8 . 38) 0 . 290 ( 7 . 37) 0. 032 ( 0 . 81) 0. 026 ( 0 . 66) 0. 056 ( 1 . 42) 0. 042 ( 1 . 07) 0. 20 ( 0 . 51) mi n 0. 120 ( 3 . 04) 0. 090 ( 2 . 29) 3 4 19 18 8 9 14 13 top v i e w (p i n s d o w n ) 0 . 395 ( 1 0. 02) 0. 38 5 ( 9. 78 ) sq 0 . 356 ( 9 . 0 4) 0 . 350 ( 8 . 8 9) sq 0 . 048 ( 1 . 21) 0 . 042 ( 1 . 07) 0. 048 ( 1 . 21) 0. 042 ( 1 . 07) 0 . 020 (0 . 5 0 ) r 0.050 (1.27) bsc 0. 180 ( 4 . 57) 0. 165 ( 4 . 19) compliant to jedec standards mo-047aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design f i gure 40. 20-l ead p l astic l e ad ed ch ip c a rrier [ p l c c ] (p -20a) d i mensions sh o w n in inc h es and ( m m) 1 20 4 9 8 13 19 14 3 18 bottom view 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) ref 0.200 (5.08) ref 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design f i g u re 41. 2 0 - t e r m i nal l e ad les s chip carr ie r [ l c c ] (e-20a) d i mensions sh o w n in inc h es and ( m m)
ad652 rev. c | page 26 of 28 ordering guide model gain drift, 100 khz 1 mhz linearity (% ) specified temperature range package options 1 ad652jp 50 ppm/c max 0.02 max 0c to +70c plcc (p-20a) ad652jp-reel 50 ppm/c max 0.02 max 0c to +70c plcc (p-20a) ad652jp-reel7 50 ppm/c max 0.02 max 0c to +70c plcc (p-20a) ad652kp 25 ppm/c max 0.005 max 0c to +70c plcc (p-20a) ad652kp-reel 25 ppm/c max 0.005 max 0c to +70c plcc (p-20a) ad652aq 2 50 ppm/c max 0.02 max ?40c to +85c cerdip (q-16) ad652bq 2 25 ppm/c max 0.005 max ?40c to +85c cerdip (q-16) ad652se/883b 2 50 ppm/c max 0.02 max ?55c to +125c lcc (e-20a) ad652sq 2 50 ppm/c max 0.02 max ?55c to +125c cerdip (q-16) ad652sq/883b 2 50 ppm/c max 0.02 max ?55c to +125c cerdip (q-16) 1 p = plastic leaded chip carrier; q = cerdip, e = leadless chip carrier. 2 for details on grade and package offerings screened in accordance with milstd-883, re fer to the analog devices military produc ts databook or current ad652/883 data sheet.
ad652 rev. c | page 27 of 28 notes
ad652 rev. c | page 28 of 28 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c00798C0 C 5/04(c)

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